The present invention relates to a novel structure of a static induction thyristor (hereinafter referred to as an "SI thyristor") and, more particularly, to a MOS composite static induction thyristor in which a MOS transistor, a diode and an SI thyristor are integrated onto a single monolithic chip.
In recent years, various MOS controlled power devices or MOS gated power devices such as MGT, MCT, EST, and DMT have been proposed. However, these MOS composite devices have, as a main thyristor unit, a conventional device such as GTO. Since ON-voltage of these MOS composite devices is finally determined by the characteristics of the main thyristor unit, prior art MOS composite devices having a conventional thyristor such as GTO has disadvantage that the ON-voltage and conduction loss are high. Further, these conventional MOS composite devices have the disadvantage that it is difficult to use the devices at high frequency.
In view of the above, a MOS composite SI thyristor, or MOS controlled SI thyristor (MCSITH), in which high efficiency and high-speed operation are expected and which comprises, as a main thyristor unit, an SI thyristor unit. Having low ON-voltage and conduction loss and high frequency operation and high speed switching, has already been proposed by the Applicant of the present invention in Japanese Patent Application No. HEI 2-95251 (Japanese Patent Laid-Open No. HEI 3-292770). The MCSITH has a structure in which a MOS transistor is integrated at a location between a gate and a cathode of a normally-off SI thyristor, as shown in FIG. 20 and FIG. 21 (a cross-sectional view taken along a line A--A in FIG. 20) of the attached drawings.
FIG. 20 is a top plan view, while FIG. 21 is a cross-sectional view taken along a line A--A in FIG. 20. As shown in FIGS. 20 and 21, an SI thyristor is formed in which an n.sup.+ region 23 is a cathode, a p.sup.+ region 21 is an anode, a p.sup.+ region 31 under a floating condition is a gate, and an n.sup.- region 22 is a channel. A p.sup.+ region 31 simultaneously serves as the source of the pMOS transistor in which a p.sup.+ region 32 is the drain and a polycrystalline silicon layer 25 is the gate electrode.
The MCSITH is turned on by a positive potential applied to the capacitance formed by the polycrystalline silicon layer 25 and an oxide film 26, which that is an insulating film provided above the p.sup.+ gate region 31 to reduce the height of a potential barrier formed in the n.sup.- channel region 22 by means of capacitive coupling (static induction effects). The MCSITH is turned off when the pMOS transistor is conducted to short-circuit the p.sup.+ gate region 31 to the n.sup.+ cathode region 23, to withdraw a hole through the p.sup.+ gate region 31.
However, this MCSITH has the following disadvantages. If the impurity concentration of the n.sup.- channel region 22 is brought to approximately 10.sup.13 cm.sup.-3 to give the main thyristor unit a normally-off characteristic, the spacing between the adjacent p.sup.+ gate regions 31 must be equal to or less than approximately 6 .mu.m. Assuming that the diffusion width of the n.sup.+ cathode stripped region 23 is 2 .mu.m, the interval between the n.sup.+ cathode region 23 and the p.sup.+ gate region 31 must then be narrowed to 2 .mu.m. Accordingly, a fine processing technique is required to merge a MOS transistor between the n.sup.+ cathode region 23 and the p.sup.+ gate region 31. For this reason, manufacturing is difficult, and a yield is low.